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TSMC Roadmap Lays Out Superior CoWoS Packaging Applied sciences, Prepared For Subsequent-Gen Chiplet Architectures & HBM3 Reminiscence

TSMC has laid out its superior packaging know-how roadmap and showcased its next-gen CoWoS options that are prepared for next-gen chiplet architectures and reminiscence options.

TSMC Lays Out Its Superior CoWoS Packaging Expertise Roadmap, 2023 Design Prepared For Chiplet & HBM3 Architectures

The Taiwanese-based semiconductor big has gained fast progress in deploying superior chip packaging applied sciences within the business. Inside a decade, the corporate has launched 5 completely different generations of CoWoS (Chip-on-Wafer-on-Substrate) packages which can be at present deployed or being deployed in client and server house.

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The corporate expects to launch its Gen 5 CoWoS packaging resolution later this yr which is able to push the transistor rely by 20x over the third Gen packaging resolution. The brand new bundle will include an interposer space enhance of three instances, 8 HBM2e stacks for as much as 128 GB capacities, a model new TSV resolution, Thick CU interconnect, and a brand new TIM (Lid bundle). Essentially the most notable resolution that can make use of the Gen 5 packaging know-how from TSMC is specifically AMD’s MI200 ‘Aldebaran’ GPU.

The AMD Aldebaran GPU would be the first MCM GPU fabricated and produced over at TSMC. The GPU shall be powered by AMD’s CDNA 2 structure and is predicted to rock some insane specs similar to over 16,000 cores and 128 GB of HBM2E reminiscence. NVIDIA’s Hopper GPU would even be making use of an MCM chiplet structure and is predicted to be produced at TSMC. This GPU is predicted to launch in 2022 so we are able to count on NVIDIA to leverage from the Gen 5 resolution too.

By Gen 6, TSMC may have a bigger reticle space to combine extra chiplets and extra DRAM packages. The bundle design has not but been finalized by TSMC expects to deal with as much as 8 HBM3 DRAM and two compute chiplet dies on the identical bundle. TSMC can also be going to supply the newest SOC thermal resolution within the type of Metallic Tim which is predicted to lower the bundle thermal resistance to 0.15x over Gel TIM utilized in 1st Gen. That is nonetheless far off and shall be designed for merchandise that shall be manufactured on the N3 course of node so we’re taking a look at both CDNA 3 (MI300) or Ampere Subsequent Subsequent.