Intel has disclosed the primary data relating to its Sapphire Rapids-SP Xeon CPUs which will likely be that includes HBM2E reminiscence stacks alongside the principle core dies in a multi-chiplet design.
Intel Sapphire Rapids-SP Xeon CPUs Pack 4 HBM2E Dies With 8-Hello Stacks In A Chiplet Design, Fused Collectively With Predominant Core Dies Utilizing EMIB
We have now already detailed Intel’s Sapphire Rapids-SP Xeon CPUs earlier however primarily based on the brand new data printed throughout HotChips 33, it seems to be just like the blue workforce is disclosing just a few extra tidbits relating to its next-gen Xeon CPUs.
In response to Intel, the Sapphire Rapids-SP will are available two bundle variants, a normal, and an HBM configuration. The usual variant will function a chiplet design composed of 4 XCC dies that can function a die measurement of round 400mm2. That is the die measurement for a singular XCC die and there will likely be 4 in complete on the highest Sapphire Rapids-SP Xeon chip. Every die will likely be interconnected through EMIB which has a pitch measurement of 55u and a core pitch of 100u.
The usual Sapphire Rapids-SP Xeon chip will function 10 EMIB interconnects and the complete bundle will measure at a mighty 4446mm2. Transferring over to the HBM variant, we’re getting an elevated variety of interconnects which sit at 14 and are wanted to interconnect the HBM2E reminiscence to the cores.
The 4 HBM2E reminiscence packages will function 8-Hello stacks so Intel goes for no less than 16 GB of HBM2E reminiscence per stack for a complete of 64 GB throughout the Sapphire Rapids-SP bundle. Speaking concerning the bundle, the HBM variant will measure at an insane 5700mm2 or 28% bigger than the usual variant. In comparison with the not too long ago leaked EPYC Genoa numbers, the HBM2E bundle for Sapphire Rapids-SP would find yourself 5% bigger whereas the usual bundle will likely be 22% smaller.
- Intel Sapphire Rapids-SP Xeon (Commonplace Package deal) – 4446mm2
- Intel Sapphire Rapids-SP Xeon (HBM2E Package deal) – 5700mm2
- AMD EPYC Genoa (12 CCD Package deal) – 5428mm2
Intel additionally states that the EMIB hyperlink gives twice the bandwidth density enchancment and 4 occasions higher energy effectivity in comparison with commonplace bundle designs.
Intel additionally detailed the bundle and die measurement of its flagship Ponte Vecchio GPU primarily based on the Xe-HPC structure. The chip will consist of two tiles with 16 energetic dies per stack. The utmost energetic high die measurement goes to be 41mm2 whereas the bottom die measurement which can also be known as the ‘Compute Tile’ sits at 650mm2. The Ponte Vecchio GPU makes use of 8 HBM 8-Hello stacks and comprises a complete of 11 EMIB interconnects. The entire Intel Ponte Vecchio bundle would measure 4843.75mm2.
