AMD Unveils Subsequent-Gen EPYC Milan-X CPUs, First To Function 3D V-Cache Tech With Insane 804 MB Cache

AMD has formally unveiled its first server product to ship with 3D V-Cache expertise, the third Gen EPYC Milan-X. The subsequent-generation Zen 3 CPUs retain the excellent Zen 3 core structure and additional improve efficiency in quite a lot of compute-intensive workloads via enhance cache.

AMD Unveils Milan-X: That includes Zen 3 Cores With Enhanced 3D V-Cache Stack Design For Up To 804 MB Cache Per Chip

The AMD EPYC Milan-X lineup is not any thriller, we already noticed the chips listed at a number of retailers & preliminary specs had been listed too. Now we all know the precise core clocks and the quantity of cache that the brand new Zen 3 chips with 3D V-Cache vertical chiplets stacking expertise will supply for server clients.

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AMD EPYC Milan-X server CPU lineup will consist of 4 processors. The EPYC 7773X options 64 cores and 128 threads, the EPYC 7573X options 32 cores and 128 threads, the EPYC 7473X options 24 cores and 48 threads whereas the EPYC 7373X options 16 cores and 32 threads. The fashions together with their OPN codes are:

• EPYC 7773X 64 Core (100-000000504)
• EPYC 7573X 32 Core (100-000000506)
• EPYC 7473X 24 Core (100-000000507)
• EPYC 7373X 16 Core (100-000000508)

The flagship AMD EPYC 7773X will rock 64 cores, 128 threads and have a most TDP of 280W. The clock speeds might be maintained at 2.2 GHz base and three.5 GHz enhance whereas the cache quantity will drive as much as an insane 768 MB. This consists of the usual 256 MB of L3 cache that the chip options so primarily, we’re taking a look at 512 MB coming from the stacked L3 SRAM which signifies that every Zen 3 CCD will characteristic 64 MB of L3 cache. That is an insane 3x enhance over the prevailing EPYC Milan CPUs.

The second mannequin is the EPYC 7573X which options 32 cores and 64 threads with a 280W TDP. The bottom clock is maintained at 2.8 GHz and the enhance clock is rated at as much as 3.6 GHz. The full cache is 768 MB for this SKU too. Now curiously, you need not have 8 CCDs to succeed in 32 cores as that may be achieved with a 4 CCD SKU too however contemplating that you just’d want double the quantity of stack cache to succeed in 768 MB, that does not seem like a really economical choice for AMD and therefore, even the lower-core rely SKUs could be that includes the complete 8-CCD chips.

With that mentioned, we have now the EPYC 7473X which is a 24 core and 48 thread variant with a 2.8 GHz base and three.7 GHz enhance clock and a TDP of 240W whereas the 16 core and 32 thread EPYC 7373X is configured at a 240W TDP with a base clock of three.05 GHz and three.8 GHz enhance clock and  768 MB of cache.

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AMD EPYC Milan-X 7003X Server CPU (Preliminary) Specs:

A single 3D V-Cache stack would incorporate 64 MB of L3 cache that sits on prime of the TSV’s already featured on current Zen 3 CCD’s. The cache will add upon the prevailing 32 MB of L3 cache for a complete of 96 MB per CCD. AMD additionally acknowledged that the V-Cache stack can go as much as 8-hi which suggests a single CCD can technically supply as much as 512 MB of L3 cache along with the 32 MB cache per Zen 3 CCD. So with a 64 MB of L3 cache, you possibly can technically stand up to 768 MB of L3 cache (8 3D V-Cache CCD stacks = 512 MB) which might be a mammoth enhance in cache measurement.

3D V-Cache may simply be one side of the EPYC Milan-X lineup. AMD may introduce quicker clocks as 7nm continues to mature and we are able to see a lot quicker efficiency from these stacked chips. As for efficiency, AMD showcased a 66% efficiency uplift in RTL verifications with Milan-X versus the usual Milan CPU. A stay demo showcased how Synopsys VCS Purposeful verification take a look at was accomplished by Milan-X 16-core SKU a lot quicker than the non-X 16 core SKU.

AMD has introduced that Milan-X could have broad platform availability via their companions reminiscent of CISCO, DELL, HPE, Lenovo, and Supermicro whereas the launch is deliberate for Q1 of 2023.

AMD EPYC CPU Households: